FPGA & RTL Design Engineer | 4+ Yrs | Verilog, VHDL, SystemVerilog, Vivado
I design, verify and debug reliable digital systems for startups, researchers and engineers worldwide.
Services:
• FPGA Design (Vivado, Quartus, Vitis HLS)
• RTL Coding (Verilog, SystemVerilog, VHDL)
• Testbenches, UVM, ModelSim, QuestaSim
• SoC / Zynq / MicroBlaze, AXI, I2C, SPI, UART
• PetaLinux, TCL, Git, RFSoC, ADRV9001
• PCB (Altium, KiCad), MATLAB, DSP
Boards: Nexys A7, Basys 3, Zybo, ZedBoard, ZC706.
Hardware Engineer at SWARM, Riyadh. B.Sc. EE, IIUI.
Clean code, free consultation, on-time delivery.... Saiba mais