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waleed_ee

Waleed Hassan

@waleed_ee

FPGA Design VHDL Verilog MATLAB and Python

Paquistão
Inglês, Urdu
Algumas informações são exibidas no idioma inglês.
Sobre mim
I design and verify digital hardware — RTL in VHDL and Verilog, with testbenches that prove the design actually works. My work covers combinational and sequential logic, finite state machines, UART/SPI controllers, datapaths and processor cores. I recently built a 5-stage pipelined RISC-V processor in VHDL with configurable branch prediction, verified against a Python reference model. Clean, commented, synthesizable code, plus simulation waveforms so you can see it run. Message me your spec before you order and I'll tell you honestly whether I can do it.... Saiba mais

Habilidades

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waleed_ee
Waleed Hassan
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Sistemas Incorporados e IoT
I will write vhdl verilog rtl code with testbench and vivado simulation