r
ramishjvd

Muhammad Ramish

@ramishjvd

ASIC Digital Design and Verification Engineer

Paquistão
Inglês, Urdu
Algumas informações são exibidas no idioma inglês.
Sobre mim
I'm a digital design and verification engineer with 3+ years of ASIC and FPGA experience. I mostly work in SystemVerilog, with Python and C++ for reference models and scripting. I've used Synopsys VCS, Cadence Xcelium and Vivado for simulation, and I'm comfortable with AXI4, RISC-V and lint cleanup. I can build testbenches from scratch, debug failing RTL from waveforms, write Makefile-based flows, and model behaviour in Python before RTL. I am well equipped for both verification and design related tasks.... Saiba mais

Habilidades

r
ramishjvd
Muhammad Ramish
offline • 
Tempo médio de resposta: 1 hora

Conheça meus serviços

Sistemas Incorporados e IoT
I will design synthesizable rtl and systemverilog uvm testbench
A partir deUS$ 50 /projetoMais detalhes
API e Integrações
I will build your python project from start to end with oop code
A partir deUS$ 40 /projetoMais detalhes

Experiência profissional

IRADA_Foundation

ASIC Digital Design and Verification Engineer | System Architect

IRADA Foundation • Período integral

Jan 2026 - Present • 9 mos

Led Development of ASIC True Random Number Generator Led Development of ASIC Direct Digital Synthesizer Worked on Project Management Documentation

Barcelona_Supercomputing Center

RE2: Vector Processing Unit Engineer

Barcelona Supercomputing Center • Período integral

Jul 2025 - Nov 2025 • 4 mos

• Worked on the RISCV Vector Processing Unit (VPU) microarchitecture within the DARE project

Xcelerium

Digital Design and Verification Engineer

Xcelerium • Período integral

Apr 2023 - Jun 2025 • 2 yrs 2 mos

Led Development of Vector Load Store Unit for RISCV Vector Extension Led Verification of Multi-Issue Pipelined RISCV Scalar Unit Led Addition of RISCV Bit Manipulation Instructions in Multi-Issue Pipelined Scalar Unit Led Verification of AXI-4 Compliant Memory SubSystem