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@poornachandra_r
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I'm a freelance VLSI engineer with experience in digital design, RTL coding, and functional verification for ASIC and FPGA projects. I specialize in end-to-end hardware development, from architecture design to verification and synthesis, with strong expertise in Verilog, SystemVerilog, UVM, and industry-standard EDA tools like Synopsys, Cadence, and Mentor Graphics. Whether you need support with RTL design and testbench creation
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Programação e Tecnologia
I will do rtl design and verification using verilog, systemverilog
