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Português
$
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Muhib A
@muhib_17
Student
Bangladesh
Inglês
Sobre mim
Hello! I am Muhib, an undergraduate student in Electronics and Communication Engineering with 3 years experience and expertise in Digital logic design , RTL design with Verilog HDL , Design Simulation.I also have expertise in using tools like Proteus, Logisim , Modelsim.I can assist you in designing , debugging and simulating digital circuits as well as hardware implementation using Verilog.
Habilidades
Muhib A
offline •
Conheça meus serviços
Programação e Tecnologia
I will assist you with digital logic design tasks, lab works and assignments
Programação e Tecnologia
I will design debug and simulate verilog rtl projects for fpga
