Ver categorias
Explorar
Fiverr Pro
Português
$
USD
Jahnavi Bingi
@jahnavi_bingi
Verilog RTL, FPGA Design Engineer
Índia
Inglês, Telugu, Hindi
Sobre mim
I am an Electronics and Communication Engineering student focused on Verilog RTL design, FPGA development, and digital system design.
I work with synthesizable Verilog HDL and have hands-on experience developing and verifying digital modules using tools such as Xilinx Vivado. My project experience includes DMA controllers, UART communication, priority queue architectures, and processor-related RTL design.
I can help with RTL module development, FSMs, FIFOs, UART, counters, registers, testbenches, simulation, debugging, and other digital design tasks.
Habilidades
Jahnavi Bingi
offline •
Tempo médio de resposta: 1 hora
Conheça meus serviços
Sistemas Incorporados e IoT
I will design synthesizable verilog rtl modules
