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farhan2207

Farhan Nabi

@farhan2207

Engineer who makes complicated work clear

Paquistão
Inglês, Urdu
Algumas informações são exibidas no idioma inglês.
Sobre mim
I am an engineer who explains things clearly. That is the whole job. 20+ years across digital design, embedded systems, teaching and programme operations. Full-time Verilog RTL on Xilinx Zynq-7000, including an HMAC/SHA-256 core at 110 MHz. University instructor in FPGA and digital logic. 25+ workshops designed and delivered, some to 350+ people. Two kinds of work here: - Verilog RTL — debugging, testbenches, documentation - Making work understandable — SOPs, process reviews, training design, technical decks Written scope. Early delivery. An honest no when I cannot do something.... Saiba mais

Habilidades

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farhan2207
Farhan Nabi
offline • 
Tempo médio de resposta: 1 hora

Conheça meus serviços

Sistemas Incorporados e IoT
I will debug and fix your verilog rtl code and prove the fix
A partir deUS$ 15 /projetoMais detalhes
Redação Técnica
I will write clear technical documentation for your hardware product
A partir deUS$ 25 /projetoMais detalhes

Experiência profissional

DPL

Organization Development Lead

DPL • Período integral

Aug 2025 - Mar 2026 • 7 mos

Documented and coordinated internal programmes across teams. Converted leadership initiatives into written execution plans with schedules, owners and follow-ups. Produced reports, dashboards and summaries for leadership, and built the tracking spreadsheets behind them.

Independent

Founder & Learning Experience Designer

Independent • Período integral

Sep 2024 - Sep 2025 • 1 yr

Designed and delivered 25+ workshops and structured programmes covering goal alignment, decision-making, creativity and problem-solving. Wrote all the material, from participant workbooks to step-by-step facilitation guides. Facilitated groups from 5 people to 350+. Built reusable frameworks that turned broad ideas into practical activities.

Powersoft19

Senior Embedded Systems Engineer

Powersoft19 • Período integral

Dec 2021 - Jun 2024 • 2 yrs 6 mos

Designed and implemented Verilog RTL on the Xilinx Zynq-7000 platform. Built an HMAC/SHA-256 cryptographic core synthesised at 110 MHz. Translated a SOGI-PLL algorithm from C into synthesisable Verilog. Designed FSM and data-path architectures for real-time signal processing. Wrote the technical documentation for my own designs, clear enough that they could be modified months later without guesswork.