a
avanthikarajend

Avanthika

@avanthikarajend

I will write professional Verilog and VHDL code for your FPGA projects

Índia
Inglês, Tâmil
Algumas informações são exibidas no idioma inglês.
Sobre mim
Welcome! I specialize in digital logic design using Verilog, VHDL, and SystemVerilog. I transform circuit requirements, block diagrams, and specs into clean, synthesisable RTL code optimized for FPGAs and ASICs. What I offer: - Verilog/VHDL RTL design - Finite State Machines (FSM) - Testbenches & verification - Tool support (Vivado, Quartus, EDA Playground) Every delivery includes fully structured code, inline comments, and documentation. Let's bring your hardware designs to life—send your project specs to get started today!... Saiba mais

Habilidades

a
avanthikarajend
Avanthika
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Tempo médio de resposta: 1 hora

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Portfólio

Experiência profissional

Self_Employed

Freelance FPGA / RTL Design Engineer

Self Employed • Autônomo

Jun 2024 - Jan 2025 • 7 mos

- Developed and delivered synthesisable RTL code in Verilog and VHDL based on client specifications. - Designed custom combinational logic circuits, multi-bit adders, multiplexers, and decoders. - Constructed robust Finite State Machines (FSM) for sequential control logic and sequence detection. - Wrote functional testbenches to verify digital designs and analyze simulation waveforms. - Utilized industry toolchains including Xilinx Vivado, Intel Quartus Prime, and ModelSim for verification. - Provided clean, well-commented hardware code along with comprehensive design documentation.