Abdullah T

@abdullaht25

I will design and debug Verilog SystemVerilog RTL modules and create testbenches

Paquistão

Inglês, Urdu, Hindi

Algumas informações são exibidas no idioma inglês.

Sobre mim

Hi, I'm Abdullah Tahir, a Computer Engineer specializing in Digital IC Design and RTL development. I work with Verilog, SystemVerilog, digital logic, simulation, and verification for FPGA and ASIC-oriented projects. My experience includes FSMs, ALUs, counters, registers, datapaths, and control units. I focus on clean, synthesizable code, proper testing, and organized project delivery. Feel free to contact me with your requirements before placing an order. ... Saiba mais

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